1. Field of the Invention
The present invention generally relates to semiconductor integrated circuits, and particularly relates to a semiconductor integrated circuit which has cross-talk noise thereof reduced by shielding wire lines.
2. Description of the Related Art
In electric circuits, inductance coupling and capacitance coupling between signal lines cause cross-talk noise. The greater the inductance coupling and capacitance coupling between lines, the greater the cross-talk noise is. In semiconductor devices such as large-scale integrated circuits, inductance coupling and capacitance coupling between lines increase as the circuit density increases thereby causing noise to appear more conspicuously. In order to reduce cross-talk noise caused by the inductance and capacitance coupling, shielding wire lines are used.
Use of shielding wire lines gives rise to problems in that they have relatively large wiring resistance per unit length.
First, large wiring resistance results in electric charging and discharging in the shielding wire lines being slowed, thereby reducing a shielding effect.
Second, when a shielding wire line is connected to the ground voltage or to the power supply voltage at several points along the line, an excessively large current runs through the shielding wire line, causing the problem of E-MIG (electro migration). The E-MIG occurs when the gradient of a power supply voltage in the LSI is ignored. For example, the power supply voltage differs between a point close to the power supply pin of the LSI and the center point of the LSI. If a shielding wire line is laid out between the points having a voltage difference, and is clipped to the power supply voltage at two end points thereof, an excessively large current ends up running through the shielding wire line. In order to circumvent this, analysis of power supply networks may be conducted to detect points where requirements of current density are not met, followed by making corrections one by one. Since there is no guarantee that this will converge, a time spent on the process of analyzing and making corrections would be regarded as a problem, especially when the speed of product development is given high priority.
Third, conventional shielding is made by providing a shield along all the extent of a shielded line. As a result, shielding wire lines consumes a wiring area to a large extent, giving rise to a problem in that an efficient layout becomes difficult to achieve. To obviate this, such measures as increasing the number of wiring layers or enlarging chip size may be conceivable. It is desirable, however, to provide efficient shielding wire lines under the given limitations of the number of wiring layers and chip-size.
Accordingly, there is a need for a method of laying out effective and efficient shielding wire lines and a semiconductor integrated circuit that has effective and efficient shielding wire lines.